Boolean Algebra Workspace

Boolean Expression Simplifier: Reduce Any Logic Expression Instantly

Simplify boolean algebra expressions in seconds. Enter SOP or standard notation, apply De Morgan’s laws, find prime implicants with Quine–McCluskey reduction, and generate the truth table plus gate network automatically.

Simplify an Expression See How It Works

ブール式の入力

AND · * OR + | NOT ' !

例:

簡略化された表現

結果はここに表示されます

真理値表

ここに真理値表が表示されます

ゲートネットワーク

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Technical Architecture

Boolean Algebra Simplification & Quine-McCluskey Reduction Architecture

Systematic algebraic reduction, prime implicant extraction, and minimal two-level gate synthesis.

The Boolean Expression Simplifier is an advanced symbolic and tabular logic optimization suite designed for digital electronics students, computer engineers, and hardware architects. In digital circuit design, unoptimized boolean expressions translate directly into excessive logic gates, increased silicon die footprint, higher propagation delays, and elevated dynamic power dissipation. This engine processes any arbitrary boolean algebraic statement—accepting sum-of-products (SOP), product-of-sums (POS), and arbitrary grouped parenthetical expressions—and algorithmically reduces it to its provably minimal equivalent form using formal Boolean theorems and the Quine-McCluskey tabular reduction method.

While 2-to-4 variable expressions are traditionally taught using manual Karnaugh maps (K-maps), visual grouping methods quickly become error-prone, subjective, and practically intractable when scaling to 5 variables or when handling complex don't-care conditions. The Quine-McCluskey algorithm eliminates human visual error by systematically converting minterms into binary representations, grouping them by Hamming weight (the count of binary 1s), and exhaustively performing single-bit adjacency merges. It automatically identifies all prime implicants, isolates essential prime implicants, and solves the minimal set-cover problem using Petrick's method or greedy heuristic reduction.

Beyond symbolic algebraic output, this tool bridges the gap between abstract mathematical equations and physical digital circuitry. Every minimized Sum-of-Products expression is directly translated into a clean, two-level AND-OR gate network or transformed into universal NAND-NAND logic using De Morgan's identities. The tool also detects static-1 hazards and generates the complete truth table, allowing engineers and students to inspect the exact input-output behavior across all 2^n binary permutations and verify logical equivalence before committing to hardware.

Engineering Capabilities

Quine-McCluskey Solver

Provably minimal Sum-of-Products (SOP) derivation via exhaustive tabular adjacency grouping.

Prime Implicant Table

Automated identification of essential prime implicants and minimal set cover resolution.

Gate Network Synthesis

Direct translation from minimized equations into two-level AND-OR and universal NAND-NAND schematics.

Axiomatic Law Verification

Algorithmic application of De Morgan's laws, consensus theorem, absorption, and idempotence.

Algebraic Foundations

Fundamental Boolean Identities & Axioms

Core algebraic laws automatically applied during canonical expansion and term minimization.

Identity Name	Algebraic Formulation	Engineering Impact
De Morgan 1	(A · B)' = A' + B'	NAND is equivalent to an OR with complemented inputs; enables all-NAND synthesis.
De Morgan 2	(A + B)' = A' · B'	NOR is equivalent to an AND with complemented inputs; enables all-NOR synthesis.
Absorption Law	A + A · B = A	Eliminates redundant dependent product terms to shrink gate counts.
Consensus Theorem	A·B + A'·C + B·C = A·B + A'·C	Identifies and removes redundant consensus terms, or adds them to eliminate static-1 hazards.
Complementarity	A + A' = 1 \| A · A' = 0	Collapses opposing literals to fixed voltage rails (VCC / GND).
Idempotence	A + A = A \| A · A = A	Permits duplicating shared minterms across multiple sub-cubes without changing logic.

Workflow Guide

How to Simplify a Boolean Logic Expression: 5-Step Engineering Workflow

From complex algebraic specification to minimized, glitch-free gate implementation.

Enter Logic Expression with Standard Boolean Notation

Input your boolean function into the editor using standard algebraic syntax: use + for logical OR, * or variable adjacency for AND, apostrophe (') or ! for negation (NOT), and parentheses for operational precedence (e.g., A(B + C') + A'B).

Engineering Pro-Tip: Always verify operator precedence: NOT takes highest precedence, followed by AND, and finally OR. Explicit parentheses eliminate ambiguity.

Generate the Truth Table and Canonical Sum of Minterms

The tool parses the expression, identifies all independent variables (up to 5 inputs, A through E), and computes the full 2^n truth table. It isolates all rows where the output evaluates to 1, extracting the canonical sum of minterms (canonical Disjunctive Normal Form, Σm).

Engineering Pro-Tip: Inspecting the truth table is the fastest way to detect tautologies (output always 1) or contradictions (output always 0) before continuing.

Group Binary Minterms by Hamming Weight and Merge Adjacencies

The Quine-McCluskey engine sorts minterms into discrete groups based on the number of set bits (1s). It compares adjacent groups to identify term pairs that differ in exactly one binary position, merging them into combined terms with a dash (-) indicating the eliminated variable.

Engineering Pro-Tip: This systematic merging mimics K-map subcube grouping but eliminates the risk of missing diagonal or wrap-around corner adjacencies.

Construct Prime Implicant Chart and Select Essential Terms

Terms that cannot be merged further are marked as Prime Implicants. The tool builds a coverage matrix matching each prime implicant against the original minterms. Any prime implicant that uniquely covers at least one minterm is identified as Essential and included in the final expression.

Engineering Pro-Tip: If non-essential terms remain, the solver chooses the minimum subset of remaining prime implicants that completely covers all remaining minterms.

Synthesize Minimal Gate Network and Inspect Hardware Savings

Review the final minimal SOP equation alongside the generated two-level gate schematic. Compare the initial gate and input literal counts against the minimized architecture to quantify propagation delay reduction and transistor savings.

Engineering Pro-Tip: To build the circuit with a single IC type, apply De Morgan's laws to convert the AND-OR network directly into an all-NAND implementation.

Practical Application

Concrete Worked Example: 4-Variable Logic Minimization & Hardware Optimization

Complete reduction of a 4-input boolean function with prime implicant grouping and transistor savings analysis.

Circuit Blueprint

4-Input Combinational Function: F(A, B, C, D) = Σm(1, 3, 5, 7, 9, 11, 12, 13, 14, 15)

Reduce the 4-variable boolean expression F(A, B, C, D) = Σm(1, 3, 5, 7, 9, 11, 12, 13, 14, 15) into its minimal Sum-of-Products (SOP) form. Determine all prime implicants, isolate the essential prime implicants, eliminate redundant terms, and calculate the physical gate count and transistor reduction compared to the unsimplified canonical equation.

Minterm Coverage & Hardware Mapping

Ref / Term	Logic Stage	Binary / Algebraic Spec	Functional Role
Canonical SOP	Unreduced Canonical Equation	10 Minterms: m(1,3,5,7,9,11,12,13,14,15)	Requires 10 4-input AND gates + 1 10-input OR gate (54 gate inputs, 108 CMOS transistors)
Group 1 Prime	8-Minterm Octet Implicant	m(1,3,5,7,9,11,13,15) -> Bit pattern: - - - 1	Reduces to single literal D (eliminates variables A, B, and C entirely)
Group 2 Prime	4-Minterm Quad Implicant	m(12,13,14,15) -> Bit pattern: 1 1 - -	Reduces to product term AB (eliminates variables C and D)
Minimal SOP	Optimized Reduced Function	F = D + AB	Requires only 1 2-input AND gate + 1 2-input OR gate (3 gate inputs, 8 CMOS transistors)
Hardware Savings	Silicon & Delay Metrics	82% gate reduction, 92.6% transistor reduction	Critical path propagation delay drops from 3 gate tiers down to a single OR stage for D

Step-by-Step Synthesis & Derivation Procedure

Step 1: Binary Minterm Conversion

Convert Decimal Minterms to 4-Bit Binary Vectors

Represent each minterm in binary: m(1)=0001, m(3)=0011, m(5)=0101, m(7)=0111, m(9)=1001, m(11)=1011, m(12)=1100, m(13)=1101, m(14)=1110, m(15)=1111. Group by Hamming weight: Group 1 (one 1): m(1); Group 2 (two 1s): m(3), m(5), m(9), m(12); Group 3 (three 1s): m(7), m(11), m(13), m(14); Group 4 (four 1s): m(15).

Step 2: First-Order and Second-Order Adjacency Merges

Merge Adjacent Minterms Differing by a Single Bit

Comparing Group 1 and 2 yields pairs: (1,3)=00-1, (1,5)=0-01, (1,9)=-001. Comparing Groups 2 and 3 yields pairs: (3,7)=0-11, (3,11)=-011, (5,7)=01-1, (5,13)=-101, (9,11)=10-1, (9,13)=1-01, (12,13)=110-, (12,14)=11-0. Comparing Groups 3 and 4 yields pairs: (7,15)=-111, (11,15)=1-11, (13,15)=11-1, (14,15)=111-. Second merge combines pairs into quads and octets: (1,3,5,7,9,11,13,15) forms octet - - - 1; (12,13,14,15) forms quad 1 1 - -.

Step 3: Prime Implicant Extraction and Essential Coverage

Construct Prime Implicant Table and Verify Full Minterm Cover

The octet (- - - 1) corresponds to term D. It covers minterms 1, 3, 5, 7, 9, 11, 13, and 15. The quad (1 1 - -) corresponds to product term AB. It covers minterms 12, 13, 14, and 15. Minterm 12 and minterm 14 are covered exclusively by AB, making AB an Essential Prime Implicant. Minterm 1 is covered exclusively by D, making D an Essential Prime Implicant.

Step 4: Minimal Schematic Gate Synthesis

Map Reduced Equation F = D + AB into Hardware Gates

Connect primary input A and input B into a 2-input AND gate (e.g., 1/4 of a 74HC08). Route the output of the AND gate into input 1 of a 2-input OR gate (1/4 of a 74HC32). Connect primary input D directly into input 2 of the OR gate. The output of the OR gate produces the final function F.

Electrical & Algebraic Verification:

Truth table verification across all 16 input combinations proves exact logical equivalence: output F is 1 whenever D=1 (8 states), plus when A=1 and B=1 with D=0 (m12=1100 and m14=1110). Transistor count in CMOS drops from 108 MOSFETs to just 8 MOSFETs. Propagation delay for input D is reduced to a single OR gate delay (approx. 7ns on 74HC series), eliminating unnecessary intermediate inverter and AND stages.

Tool Comparison

When to Use Boolean Expression Simplifier vs. Alternative Methods

Compare digital logic minimization techniques across speed, accuracy, and practical gate synthesis.

Paper-and-Pencil Minimization

Manual Karnaugh Maps (K-Maps)

Strengths: Excellent pedagogical tool for developing visual intuition for 2, 3, or 4 variable adjacency.

Drawbacks: Extremely prone to human grouping slips, wrap-around corner misreads, and becomes completely unmanageable for 5 or more variables.

When to Choose: Use manual K-maps for quick classroom exercises; use Boolean Expression Simplifier for guaranteed error-free verification and multi-variable equations.

General Computer Algebra System

Wolfram Alpha

Strengths: Broad support for generic symbolic mathematics and truth table generation.

Drawbacks: Outputs abstract mathematical notation rather than electronics engineering SOP; cannot generate gate-level schematics or hardware BOM metrics.

When to Choose: Use Wolfram Alpha for pure mathematical analysis; use Boolean Expression Simplifier for digital electronics design and schematic synthesis.

Enterprise Logic Synthesis EDA

Yosys / Berkeley ABC

Strengths: Industrial-grade technology mapping for ASIC standard cells and FPGA LUT architectures.

Drawbacks: Requires command-line operation, complex TCL scripting, and Verilog HDL source files just to simplify a single combinational expression.

When to Choose: Use Yosys for full FPGA bitstream compilation; use Boolean Expression Simplifier for instant, zero-setup browser minimization and coursework validation.

For electrical engineering students, instructors, and hardware designers, the Boolean Expression Simplifier delivers the ideal combination of mathematical rigor, instant browser access, and direct schematic visualization.

よくある質問

What is the exact difference between a Prime Implicant and an Essential Prime Implicant?

A prime implicant is a rectangular grouping of minterms (of size 1, 2, 4, 8, 16...) that cannot be combined with any adjacent group to form a larger group with fewer literals. An essential prime implicant is a prime implicant that covers at least one minterm that is not covered by any other prime implicant. Every essential prime implicant must be included in any minimal Sum-of-Products solution.

How does the Quine-McCluskey algorithm guarantee the minimal Sum-of-Products (SOP)?

Unlike heuristic or visual grouping methods, the Quine-McCluskey method exhaustively compares all minterms by Hamming weight to find every possible prime implicant. It then constructs a prime implicant chart that systematically guarantees the minimum number of product terms and literals required to cover all active minterms, ensuring mathematical optimality.

Can this tool handle Don't-Care (X or d) conditions in logic simplification?

Yes. In digital logic design, certain input combinations may never occur or their output state may not matter. When specified, the simplifier treats don't-care conditions as binary 1s during the initial adjacency grouping to maximize group size and eliminate literals, but does not require them to be covered in the final essential prime implicant selection.

Why is Sum of Products (SOP) preferred over Product of Sums (POS) for circuit synthesis?

Sum-of-Products maps naturally to standard Programmable Logic Arrays (PLAs) and two-level AND-OR gate networks. Furthermore, using De Morgan's laws, an AND-OR network converts directly into an all-NAND gate circuit with identical gate counts and wiring topologies, allowing designers to build the circuit using a single inexpensive quad-NAND IC type (such as the 74HC00).

What is a static-1 logic hazard and how does boolean simplification affect circuit glitches?

A static-1 hazard occurs when an input transition between two adjacent minterms covered by different prime implicants causes a momentary false 0 spike (glitch) due to unequal gate propagation delays. While minimal SOP expressions minimize gate count, eliminating static hazards requires adding a redundant consensus prime implicant to bridge the transition boundary.

How does algebraic simplification directly reduce power and propagation delay in physical CMOS ICs?

In CMOS digital ICs, every input literal represents the gate capacitance of complementary PMOS and NMOS transistor pairs. Minimizing the boolean expression reduces total gate count and fan-in, which directly cuts dynamic switching power dissipation (P = C * V^2 * f) and minimizes capacitive load, yielding shorter propagation delays and higher maximum operating clock frequencies.